1. Field of the Invention
Example embodiments of the present invention relate to a method of forming an insulation structure and a method of manufacturing a semiconductor device using the method of forming the insulation structure. More particularly, example embodiments of the present invention relate to a method of forming an insulation structure having a uniform thickness and improved electrical characteristics, and a method of manufacturing a semiconductor device using the method of forming the insulation structure.
2. Description of the Related Art
Semiconductor memory devices are usually divided into volatile semiconductor memory devices such as dynamic random access memory (DRAM) devices or static random access memory (SRAM) devices and non-volatile semiconductor memory devices such as flash memory devices or electrically erasable and programmable read only memory (EEPROM) devices. The volatile semiconductor memory devices may lose stored data when power is off, whereas the non-volatile semiconductor memory devices may maintain stored data even when power is off. Since the stored data may be maintain in the non-volatile semiconductor memory devices for a relatively long time, the non-volatile semiconductor memory devices have been widely used in various electronic apparatuses such as digital cameras, cellular phones, MP3 players, etc.
Recently, an insulation layer having a multi-layered structure has been employed in a semiconductor memory device so as to improve electrical characteristics of the semiconductor memory device. For example, Korean Laid-Open Patent Publication No. 2002-2750 discloses a method of manufacturing a semiconductor device having an insulation layer having a multi-layered structure by an oxidation process and a nitration process.
FIGS. 1 to 5 are cross-sectional views illustrating the method of manufacturing the semiconductor device having the insulation layer according to the above Korean Laid-Open Patent Publication.
Referring to FIG. 1, an isolation layer 10 is formed on a semiconductor substrate 5 to divide the semiconductor substrate 5 into an active region and a field region.
A thermal oxidation layer 15 is formed on the semiconductor substrate 5 having the isolation layer 10. The thermal oxide layer 15 is formed by a dry thermal oxidation process or a wet thermal oxidation process. The thermal oxide layer 15 has a thickness of about 20 Å to about 50 Å based on an upper face of the semiconductor substrate 5. The thickness of the thermal oxide layer 15 is adjusted in accordance with desired electrical characteristics of the semiconductor device.
Referring to FIG. 2, a first nitrogen-containing layer 20 is formed between the semiconductor substrate 5 and the thermal oxide layer 15 and between the isolation layer 10 and the thermal oxide layer 15. The first nitrogen-containing layer 20 is formed by thermally treating the thermal oxide layer 15 under a nitrogen monoxide (NO) atmosphere or a nitrous oxide (N2O) atmosphere.
In a thermal treatment process for forming the first nitrogen-containing layer 20, nitrogen atoms are accumulated at an interface between the semiconductor substrate 5 and the thermal oxide layer 15 and at an interface between the isolation layer 10 and the thermal oxide layer 15 as arrows shown in FIG. 2. Hence, the first nitrogen-containing layer 20 is formed between the semiconductor substrate 5 and the thermal oxide layer 15 and between the isolation layer 10 and the thermal oxide layer 15. The first nitrogen-containing layer 20 may reduce a roughness of the interface between the semiconductor substrate 5 and the thermal oxide layer 15 and a roughness of the interface between the isolation layer 10 and the thermal oxide layer 15.
Referring to FIG. 3, a second nitrogen-containing layer 25 is formed on the thermal oxide layer 15 by nitrifying a surface of the thermal oxide layer 15, thereby forming an insulation layer 30 on the semiconductor substrate 5. The insulation layer 30 includes the thermal oxide layer 15, the first nitrogen-containing layer 20 and the second nitrogen-containing layer 25.
The second nitrogen-containing layer 25 is formed by performing a remote plasma process on the surface of the thermal oxide layer 15. In the remote plasma process, nitrogen atoms are accumulated at the surface of the thermal oxide layer 15 as arrows shown in FIG. 3, thereby forming the second nitrogen-containing layer 25 on the thermal oxide layer 15. The second nitrogen-containing layer 25 may prevent impurities from permeating into the insulation layer 30 in successive processes.
Referring to FIG. 4, a gate electrode layer 35 is formed on the insulation layer 30. The gate electrode layer 35 is formed using metal silicide or polysilicon doped with impurities.
Referring to FIG. 5, a gate mask (not shown) is formed on the gate electrode layer 35, and then the gate electrode layer 35 and the insulation layer 30 are successively etched using the gate mask as an etching mask. Thus, a gate structure 65 having an insulation layer pattern 55 and a gate electrode 60 is formed on the semiconductor substrate 5. The insulation layer pattern 55 includes a first nitrogen-containing layer pattern 40, a thermal oxide layer pattern 45 and a second nitrogen-containing layer pattern 50 sequentially formed on the semiconductor substrate 5.
Impurities are implanted into portions of the semiconductor substrate 5 adjacent to the gate structure 65 to form source/drain regions (not shown) at the portions of the semiconductor substrate 5. Therefore, the semiconductor device having the insulation layer 30 is formed on the semiconductor substrate 5.
As for a current non-volatile semiconductor device such as a flash memory device, an active region of a semiconductor substrate is defined by an isolation layer filling a relatively deep trench formed by partially etching the semiconductor substrate, and then a tunnel insulation layer is formed on the active region of the semiconductor substrate. Thus, the above-mentioned processes for forming the insulation layer may not be easily employed in forming the tunnel insulation layer of the current non-volatile semiconductor device. Particularly, in a flash memory device including isolation layer patterns having relatively high heights and a floating gate formed between the isolation layer patterns by a self-aligned ploy (SAP) process, tunnel insulation layers may not be uniformly formed between the isolation layer patterns on a semiconductor substrate because the semiconductor substrate may be damaged in an etching process for forming the trenches.
A current flash memory device generally includes a silicon substrate having an active region defined by isolation layer patterns, a tunnel insulation layer formed on the active region, a floating gate provided on the tunnel insulation layer, a dielectric layer formed on the floating gate and a control gate disposed on the dielectric layer. In the current flash memory device, a programming operation or an erasing operation may be accomplished by a tunneling phenomenon. That is, the programming operation may be performed by accumulating charges into the floating gate through the tunnel insulation layer, whereas the erasing operation may be carried out by removing the floating gate through the tunnel insulation layer. To properly store or erase data into or from the flash memory device, threshold voltage (Vth) distribution of memory cells in the flash memory device may be reduced as small as possible. Hence, the tunnel insulation layer may have a uniform thickness so as to desirably reduce the threshold voltage distribution of the memory cells in the flash memory device. In other words, a central portion of the tunnel insulation layer may have a thickness substantially the same as that of a peripheral portion including an edge of the tunnel insulation layer. That is, a thickness difference between the central portion and the peripheral portion may be reduced. However, the tunnel insulation layer may not be uniformly formed on the silicon substrate because of the damage to the silicon substrate generated in an etching process for forming trenches. Particularly, the thickness of the edge of the tunnel insulation layer may become unfortunately thin so that the threshold voltage distribution of the memory cells may be considerably increased.
Meanwhile, the charges may not be trapped in the tunnel insulation layer during the programming operation and the erasing operation in order to improve endurance of the flash memory device and to enhance reliability of the flash memory device. Namely, charge trapping sites may not be undesirably generated in the tunnel insulation layer, to thereby increase the endurance and the reliability of the flash memory device. In the above-mentioned flash memory device, however, the charge trapping sites may be considerably generated in the tunnel insulation layer during the programming and erasing operations of the flash memory device even though the tunnel insulation layer may be formed using a dielectric material having a high dielectric constant such as metal oxide.